Specialists in Silicon Design and Verification
+353 91 558090 (Galway)
+353 1 5553844 (Dublin)
info@crevinn.com

In tandem with our Top-Down Fletcher Design Methodology, CreVinn’s Development Process places an equal emphasis on our Verification Methodology.  An integral part of any Design Services project was the creation of the Verification Plan and the development of Verification Components such as High-level behavioural Model, Bus Functional Models and Interface Transactors and Cycle-accurate C-based models.

 

To help achieve our verification aims, CreVinn was an keen adaptor of System Verilog based verification and was an early licensee of VCS NTB (Native Testbench) from Synopsys and later moved to adopt the VMM methodology from Synopsys.  CréVinn developed a set of Verification Functions, known as  our CVM Library (Consise Verification Methodology) that we used to augment the VMM  library and support the rapid development of Verification Testbenches, providing several functions missing from early VMM releases.

 

CréVinn has been keenly following the latest trends in Verification Methodologies and CréVinn’s Engineering Team has now many years of experience in the latest Verification Methodologies from VMM and OVM to UVM and have worked on several large verification projects for our Customers, covering areas from Networking, Computer Systems to Power Control.

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