Specialists in Silicon Design and Verification

 

For details on the following IP CréVinn IP please check the following links:

 


Design IP:

 

Dual-channel Gigabit TCP Offload Engine:                                    TOE_2G_Datasheet

 

10 Gigabit MAC compliant with IEEE 802.3ae specifications:    10G_MAC_Datasheet

 

10 Gigabit PCS core compliant with IEEE 802.3ae Clause 48:    10G_PCS_Datasheet

 

Layer2 Gigabit Ethernet Switch core:                                             L2_Gigabit_Ethernet_Switch_Datasheet

 

 

 

 

 

Verification IP:

 

AXI3, AXI4, AXI4-Lite Interconnect UVM based Verification IP:    CréVinn_UVM_AXI_VIP

 

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info@crevinn.com