Building on experience gained in developing System Verilog based Verification environments for our Design Projects, we also provide Verification Services as a separate function to Design Services, and have built up expertise within our team to cover VMM, OVM and UVM methodologies.

Our Engineers are experienced in the latest verification techniques supported by these methodologies including:

–  Efficient development of Reusable, Scalable Verification Components

–  Transaction level verification models, Bus Function Models, Stimulus Sequencers

–  Constrained Random Verification

–  Assertion based verification

–  Code Coverage and Test Analysis

–  Register Abstraction

Whether for the Verification of an IP block, Full ASIC/FPGA, SOC or multi-device system, using these methods our engineers can develop a comprehensive self-checking verification environment that will increase the speed and accuracy of verification and reduce over-all project duration.

CréVinn can offer several levels of engagement for Verification Services, ranging from providing experienced engineers to expand our customers Verification team to taking full responsibility for the development and implementation of a verification plan from initial specification to final testing.